MC912DG128A Motorola, MC912DG128A Datasheet - Page 261

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

IBDR — IIC Bus Data I/O Register
15-iicbus
MOTOROLA
RESET:
Bit 7
NOTE:
D7
0
D6
6
0
RXAK — Received Acknowledge
.
Read and write anytime
In master transmit mode, when data is written to the IBDR a data transfer
is initiated. The most significant bit is sent first. In master receive mode,
reading this register initiates next byte data receiving. In slave mode, the
same functions are available after an address match has occurred.
In master transmit mode, the first byte of data written to IBDR following
assertion of MS/SL is used for the address transfer and should comprise
of the calling address (in position D7-D1) concatenated with the required
R/W bit (in position D0).
1. Complete one byte transfer (set at the falling edge of the 9th
2. Receive a calling address that matches its own specific address in
3. Arbitration lost.
This bit must be cleared by software, writing a one to it, in the interrupt
routine.
The value of SDA during the acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates an acknowledge
signal has been received after the completion of 8 bits data
transmission on the bus. If RXAK is high, it means no acknowledge
signal is detected at the 9th clock.
0 = Acknowledge received
1 = No acknowledge received
clock).
slave receive mode.
D5
5
0
D4
4
0
Inter-IC Bus
D3
3
0
D2
2
0
MC68HC912DT128A Rev 2.0
D1
1
0
IIC Register Descriptions
Bit 0
D0
0
Inter-IC Bus
High
$00E4
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