MC912DG128A Motorola, MC912DG128A Datasheet - Page 157

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

CLKSEL — Clock Generator Clock select Register
23-clock
MOTOROLA
RESET:
Bit 7
0
0
BCSP
6
0
Read and write anytime. Exceptions are listed below for each bit.
BCSP — Bus Clock Select PLL
BCSS — Bus Clock Select Slow
MCS — Module Clock Select
BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
This bit has no effect when BCSP is set.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
BCSS
5
0
Clock Functions
4
0
0
3
0
0
Limp-Home and Fast STOP Recovery modes
MCS
2
0
MC68HC912DT128A Rev 2.0
1
0
0
Bit 0
0
0
Clock Functions
$003D
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