MC912DG128A Motorola, MC912DG128A Datasheet - Page 240

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

SP0CR1 — SPI Control Register 1
Bidirectional
Mode (MOMI or
SISO)
Register
Descriptions
Multiple Serial Interface
MC68HC912DT128A Rev 2.0
240
RESET:
When SPE=1
Bidirectional
SPC0=0
SPC0=1
Normal
Mode
Mode
SPIE
Bit 7
0
SWOM enables open drain output. PS4 becomes GPIO.
Figure 36 Normal Mode and Bidirectional Mode
SPE
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
6
0
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to
Modes.
Read or write anytime.
SPIE — SPI Interrupt Enable
SWOM enables open drain output.
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
Master Mode
SWOM
DDRS5
DDRS5
MSTR=1
5
0
or MODF status flag is set
Multiple Serial Interface
MSTR
4
0
MOMI
PS4
MO
MI
CPOL
3
0
SWOM enables open drain output. PS5 becomes GPIO.
CPHA
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
2
1
SWOM enables open drain output.
Slave Mode
DDRS4
DDRS4
SSOE
MSTR=0
1
0
Operating
LSBF
Bit 0
0
SISO
PS5
SO
SI
MOTOROLA
$00D0
18-msi