MC912DG128A Motorola, MC912DG128A Datasheet - Page 76

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MC912DG128A

Manufacturer Part Number
MC912DG128A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet

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DDRK — Port K Data Direction Register
PPAGE — (Program) Page Index Register
Resource Mapping
MC68HC912DT128A Rev 2.0
76
RESET:
RESET:
DDK7
Bit 7
Bit 7
0
0
0
6
0
0
6
0
0
PIX[2:0] — The content of the PPAGE register emulated externally.
I
Read and write: anytime.
This register determines the primary direction for each port K pin
configured as general-purpose I/O.
This register is not in the map in peripheral or expanded modes while the
EMK control bit is set.
Read and write: anytime.
This register determines the active page viewed through
MC68HC912DT128A windows.
and can be stretched when accessing external memory depending on
the EXTR0 and EXTR1 bits in the MISC register. The ECS signal is
only active when the EMK bit is set.
This content indicates which Flash module register space is in the
memory map and which 16K byte Flash memory is in the program
space. In special mode and with ROMTST bit set, the content of the
Page Index register indicates which 32K byte Flash array is in the test
program space.
0 = Associated pin is a high-impedance input.
1 = Associated pin is an output.
5
0
0
5
0
0
Resource Mapping
4
0
0
4
0
0
DDK3
3
0
3
0
0
DDK2
PIX2
2
0
2
0
DDK1
PIX1
1
0
1
0
DDK0
PIX0
Bit 0
Bit 0
0
0
MOTOROLA
8-mapping
$00FD
$00FF

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