MC912DG128A Motorola, MC912DG128A Datasheet - Page 332

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

Development Support
MC68HC912DT128A Rev 2.0
332
SPEEDUP PULSE
START OF BIT TIME
BKGD PIN
BKGD PIN
DRIVE TO
(TARGET
TARGET MCU
HOST
DRIVE AND
BCLK
MCU)
PERCEIVED
Figure 61 BDM Target to Host Serial Bit Timing (Logic 0)
Figure 60
MC68HC912DT128A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The
host holds the BKGD pin low long enough for the target to recognize it
(at least two target B cycles). The host must release the low drive before
the target MCU drives a brief active-high speed-up pulse seven cycles
after the perceived start of the bit time. The host should sample the bit
level about ten cycles after it started the bit time.
Figure 61
MC68HC912DT128A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target MC68HC912DT128A finishes it.
Since the target wants the host to receive a logic zero, it drives the
BKGD pin low for 13 BCLK cycles, then briefly drives it high to speed up
the rising edge. The host samples the bit level about ten cycles after
starting the bit time.
shows the host receiving a logic one from the target
shows the host receiving a logic zero from the target
10 CYCLES
Development Support
10 CYCLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
SPEEDUP PULSE
HC12A4 BDM TARGET TO HOST TIM 0
EARLIEST
START OF
NEXT BIT
MOTOROLA
6-dev