MC912DG128A Motorola, MC912DG128A Datasheet - Page 254

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

IBFD — IIC Bus Frequency Divider Register
IBAD — IIC Bus Address Register
Clock Stretching
IIC Register Descriptions
Inter-IC Bus
MC68HC912DT128A Rev 2.0
254
RESET:
RESET:
ADR7
Bit 7
Bit 7
0
0
0
ADR6
6
0
6
0
0
one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
The clock synchronization mechanism can be used by slaves to slow
down the bit rate of a transfer. After the master has driven SCL low the
slave can drive SCL low for the required period and then release it. If the
slave SCL low period is greater than the master SCL low period then the
resulting SCL bus signal low period is stretched.
.
Read and write anytime
This register contains the address the IIC will respond to when
addressed as a slave; note that it is not the address sent on the bus
during the address transfer
ADR7–ADR1 — Slave Address
Read and write anytime
Bit 1 to bit 7 contain the specific slave address to be used by the IIC
module.
The default mode of IIC is slave mode for an address match on the
bus.
ADR5
IBC5
5
0
5
0
ADR4
IBC4
4
0
4
0
Inter-IC Bus
ADR3
IBC3
3
0
3
0
ADR2
IBC2
2
0
2
0
ADR1
IBC1
1
0
1
0
Bit 0
Bit 0
IBC0
0
0
0
MOTOROLA
$00E1
$00E0
8-iicbus