MC912DG128A Motorola, MC912DG128A Datasheet - Page 317

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

ATD0CTL4/ATD1CTL4 — ATD Control Register 4
7-atd
MOTOROLA
RESET:
RES10
Bit 7
0
SMP1
6
0
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module
operation at breakpoint)
RES10 — 10 bit Mode
SMP1, SMP0 — Select Sample Time
the result register counter; a new sequence (non-FIFO) initiated with
a write to ATDCTL4/5 followed by a write to ATDCTL3 to set the FIFO
bit will start a FIFO sequence with the result register initialized.
Finally, which result registers hold valid data can be tracked using the
conversion complete flags. Fast flag clear mode may or may not be
useful in a particular application to track valid data.
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint is encountered. These two bits
determine how the ATD will respond when background debug mode
becomes active.
The ATD control register 4 is used to select the clock source and set
up the prescaler. Writes to the ATD control registers initiate a new
conversion sequence. If a write occurs while a conversion is in
progress, the conversion is aborted and ATD activity halts until a write
to ATDCTL5 occurs.
Used to select one of four sample times after the buffered sample and
transfer has occurred.
0 = 8 bit operation
1 = 1= 10 bit operation
Table 49 ATD Response to Background Debug Enable
SMP0
FRZ1
5
0
Analog-To-Digital Converter (ATD)
0
0
1
1
FRZ0
PRS4
0
1
0
1
4
0
Continue conversions in active background mode
PRS3
3
0
Finish current conversion, then freeze
Freeze when BDM is active
PRS2
2
0
ATD Response
Reserved
Analog-To-Digital Converter (ATD)
PRS1
MC68HC912DT128A Rev 2.0
1
0
PRS0
Bit 0
1
ATD Registers
$0064/$01E4
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