MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 128

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.4.3 Load/Store Unit (LSU)
3.4.4 Floating-Point Unit (FPU)
MPC555
USER’S MANUAL
The IU also includes the integer exception register (XER) and the general-purpose
register file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–
BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require
multiple clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so
that consecutive multiply instructions can be issued on consecutive clock cycles. Di-
vide instructions are not pipelined; an integer divide instruction preceded or followed
by an integer divide or multiply instruction results in a stall in the processor pipeline.
Note that since IMUL–IDIV and ALU–BFU are implemented as separate execution
units, an integer divide instruction preceded or followed by an ALU–BFU instruction
does not cause a delay in the pipeline.
The load/store unit handles all data transfer between the general-purpose register file
and the internal load/store bus (L-bus). The load/store unit is implemented as an inde-
pendent execution unit so that stalls in the memory pipeline do not cause the master
instruction pipeline to stall (unless there is a data dependency). The unit is fully pipe-
lined so that memory instructions of any size may be issued on back-to-back cycles.
There is a 32-bit wide data path between the load/store unit and the general-purpose
register file. Single-word accesses can be achieved with an internal on-chip data RAM,
resulting in two clocks latency. Double-word accesses require two clocks, resulting in
three clocks latency. Since the L-bus is 32 bits wide, double-word transfers require two
bus accesses. The load/store unit performs zero-fill for byte and half-word transfers
and sign extension for half-word transfers.
Addresses are formed by adding the source one register operand specified by the in-
struction (or zero) to either a source two register operand or to a 16-bit, immediate val-
ue embedded in the instruction.
The FPU contains a double-precision multiply array, the floating-point status and con-
trol register (FPSCR), and the FPRs. The multiply-add array allows the MPC555 /
MPC556 to efficiently implement floating-point operations such as multiply, multiply-
add, and divide.
The MPC555 / MPC556 depends on a software envelope to fully implement the IEEE
floating-point specification. Overflows, underflows, NaNs, and denormalized numbers
cause floating-point assist exceptions that invoke a software routine to deliver (with
hardware assistance) the correct IEEE result.
To accelerate time-critical operations and make them more deterministic, the MPC555
/ MPC556 provides a mode of operation that avoids invoking the software envelope
and attempts to deliver results in hardware that are adequate for most applications, if
not in strict conformance with IEEE standards. In this mode, denormalized numbers,
NaNs, and IEEE invalid operations are treated as legitimate, returning default results
rather than causing floating-point assist exceptions.
/
MPC556
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
MOTOROLA
3-6