MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 718

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
sired, or even impossible, to add load to the lines connected to the existing system.
The development system interface of the CPU supports such a configuration.
The development system interface of the CPU uses a dedicated serial port (the devel-
opment port) and, therefore, does not need any of the regular system interfaces. Con-
trolling the activity of the system from the development port is done when the CPU is
in the debug mode. The development port is a relatively economical interface (three
pins) that allows the development system to operate in a lower frequency than the fre-
quency of the CPU. Note that it is also possible to debug the CPU using monitor de-
bugger software, for more information refer to
Support.
Debug mode is a state where the CPU fetches all instructions from the development
port. In addition, when in debug mode, data can be read from the development port
and written to the development port. This allows memory and registers to be read and
modified by a development tool (emulator) connected to the development port.
For protection purposes, two possible working modes are defined: debug mode en-
able and debug mode disable. These working modes are selected only during reset.
For more information refer to
The user can work in debug mode starting from reset or the CPU can be programmed
to enter debug mode as a result of a predefined list of events. These events include
all possible interrupts and exceptions in the CPU system, including the internal break-
points, together with two levels of development port requests (masked and non-
masked) and one peripheral breakpoint request that can be generated by any one of
the peripherals of the system (including internal and external modules). Each event
can be programmed either to be treated as a regular interrupt that causes the machine
to branch to its interrupt vector, or to be treated as a special interrupt that causes de-
bug mode entry.
When in debug mode an rfi instruction will return the machine to its regular work mode.
The relationship between the debug mode logic to the rest of the CPU chip is shown
in the following figure.
/
MPC556
21.4.1.1 Debug Mode Enable vs. Debug Mode Disable
DEVELOPMENT SUPPORT
Rev. 15 October 2000
21.6 Software Monitor Debugger
MOTOROLA
21-22