MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 248

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.1.2 Hard Reset
7.1.3 Soft Reset
MPC555
USER’S MANUAL
If the MPC555 / MPC556 is in single-chip mode and limp mode is enabled, the internal
PLL is not required to be locked before the chip exits power-on reset.
After exiting the power-on reset state, the MCU continues to drive the HRESET and
SRESET pins for 512 system clock cycles. When the timer expires (after 512 cycles),
the configuration is sampled from data bus pins, if required (see
Configuration) and the MCU stops driving the HRESET and SRESET pins. In addi-
tion, the internal MODCK[1:3] values are sampled.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns
are rejected. The internal PORESET signal asserts only if the PORESET pin asserts
for more than 100 ns.
HRESET (hard reset) is an active low, bi-directional I/O pin. The MPC555 / MPC556
can detect an external assertion of HRESET only if it occurs while the MCU is not as-
serting reset.
When the MPC555 / MPC556 detects assertion of the external HRESET pin or a
cause to assert the internal HRESET line, is detected the chip starts to drive the
HRESET and SRESET for 512 cycles. When the timer expires (after 512 cycles) the
configuration is sampled from data pins (refer to
the chip stops driving the HRESET and SRESET pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After detecting the negation of
HRESET or SRESET, the MCU waits 16 clock cycles before testing the presence of
an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are
rejected. The internal HRESET will be asserted only if HRESET is asserted for more
than 100 ns.
The HRESET is an open collector type pin.
SRESET (soft reset) is an active low, bi-directional I/O pin. The MPC555 / MPC556
can only detect an external assertion of SRESET if it occurs while the MPC555 /
MPC556 is not asserting reset.
When the MPC555 / MPC556 detects the assertion of external SRESET or a cause to
assert the internal SRESET line, the chip starts to drive the SRESET for 512 cycles.
When the timer expires (after 512 cycles) the debug port configuration is sampled from
the DSDI and DSCK pins and the chip stops driving the SRESET pin. An external pull-
up resistor should drive the SRESET pin high. After the MPC555 / MPC556 detects
the negation of SRESET, it waits 16 clock cycles before testing the presence of an ex-
ternal soft reset.
/
MPC556
Rev. 15 October 2000
RESET
7.5.1 Hard Reset
Configuration) and
7.5.1 Hard Reset
MOTOROLA
7-2