MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 218

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MPC555
USER’S MANUAL
ority levels. Each one of the SIU internal interrupt sources, as well as the interrupt re-
quests generated by the IMB3 modules, can be assigned by the software to any one
of those eight interrupt priority levels.
The same interrupt request signal that is generated within the RCPU is optionally driv-
en on the IRQ_OUT pin. This pin may be used in peripheral mode, in which the internal
processor is shut off and the internal modules are accessed externally.
The IMB3 interrupts are controlled by the UIMB. The IMB3 provides 32 interrupt levels.
Any interrupt source can be configured to any IMB3 interrupt level. The 32-bit UIPEND
register in the UIMB holds the pending IMB3 interrupt requests. IMB3 interrupt request
levels zero to six are mapped to USIU interrupt levels zero to six, respectively. IMB3
interrupt request levels seven to 31 are mapped to USIU request level seven. The user
must read the UIPEND register to determine the actual source of the interrupt. Refer
to
Figure 6-5
12.4 Interrupt Operation
/
MPC556
If the same interrupt level is assigned to more than one source, soft-
ware must read the appropriate status bits in the appropriate UIMB3
registers to determine which interrupt was asserted.
illustrates the operation of the interrupt controller.
SYSTEM CONFIGURATION AND PROTECTION
for more information.
Rev. 15 October 2000
NOTE
MOTOROLA
6-10

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