MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 567

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPIOSMDDR — MPIOSM Data Direction Register
MPIOSMDR — MPIOSM Data Register
15.13.1.2 MPIOSM Data Direction Register (MPIOSMDDR)
15.14 MIOS1 Interrupts
MPC555
USER’S MANUAL
DDR1 DDR1 DDR1 DDR1 DDR1 DDR10 DDR9 DDR8 DDR7 DDR6
MSB
MSB
Bit(s)
Bit(s)
D15
0:15
0:15
0
0
U
0
RESET:
RESET:
This read/write register defines the data direction for each implemented I/O pin of the
MPIOSM.
The MIOS1 and its submodules are capable of generating interrupts to be transmitted
to the CPU via the IMB3. Inside the MIOS1, all the information required for requesting
and servicing the interrupts are treated in two different blocks:
D14
• The interrupt control section (ICS)
1
0
U
1
DDR[15:0]
/
D[15:0]
MPC556
Name
Name
D13
2
0
U
2
D[0:4] controls the signals MPIO32B[0:4]. These functions are
shared on the MPC555 / MPC556 pins VF[0:2]/MPIO32B[0:2]
VFLS[0:1]/MPIO32B[3:4] and can be configured as the alternate
function (VF[0:2] and VFLS[0:1]). See
Control
Data BITS. These bits are read/write data bits that define the value to be driven to the pad in
output mode for each implemented I/O pin of the MPIOSM. While in output mode, a read returns
the value of the pad. Note that, when little-endian bit ordering is used, bit 0 corresponds to D15
and bit 15 corresponds to D0.
Data direction. These bits are read/write data bits that define the data direction status for each
implemented I/O pin of the MPIOSM. Note that, when little-endian bit ordering is used, bit 0 cor-
responds to D15 and bit 15 corresponds to D0.
0 = Corresponding pin is input.
1 = Corresponding pin is output.
D12
3
0
U
3
Table 15-27 MPIOSMDDR Bit Descriptions
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Register.
Table 15-26 MPIOSMDR Bit Descriptions
D11
4
0
U
4
D10
U
5
0
5
Rev. 15 October 2000
D9
U
6
6
0
D8
U
7
7
0
NOTE
D7
U
8
8
0
Description
Description
D6
U
9
15.8.1.1 MIOS1 Test and Pin
9
0
DDR5
D5
10
10
U
0
DDR4 DDR3 DDR2 DDR1 DDR0
D4
11
11
U
0
D3
12
12
U
0
D2
13
U
13
0
0x30 6102
0x30 6100
MOTOROLA
D1
14
U
14
0
15-31
LSB
LSB
D0
15
U
15
0