MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 616

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IMASK — Interrupt Mask Register
16.7.13 Interrupt Mask Register
MPC555
USER’S MANUAL
MSB
Bit(s)
Bit(s)
0
0
8:15
0:7,
RESET:
14
15
1
0
/
MPC556
WAKEINT
IMASKH,
ERRINT
IMASKL
Name
Name
2
0
BITERR[1:0]
Table 16-21 ESTAT Bit Descriptions (Continued)
3
0
00
01
10
11
IMASKH
Table 16-23 Fault Confinement State Encoding
Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a
transmit or receive error.
0 = No error interrupt request
1 = If an event which causes one of the error bits in the error and status register to be set
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the
TouCAN module is in low-power stop mode.
0 = No wake interrupt requested
1 = When the TouCAN is in low-power stop mode and a recessive to dominant transition is
IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16-
bit read or write, and IMASKH and IMASKL can be accessed with byte reads or writes.
IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buff-
ers will generate interrupts after successful transmission/reception. Setting a bit in IMASK
enables interrupt requests for the corresponding message buffer.
NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage
buffer 15.
occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt
request is generated.
detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an in-
terrupt request is generated.
4
0
Table 16-22 Transmit Bit Error Status
Table 16-24 IMASK Bit Descriptions
No transmit bit error
At least one bit sent as dominant was received as recessive
At least one bit sent as recessive was received as dominant
Not used
FCS[1:0]
CAN 2.0B CONTROLLER MODULE
5
0
1X
00
01
Rev. 15 October 2000
6
0
7
0
Bit Error Status
8
0
Error passive
Error active
Bus State
Description
Description
Bus off
9
0
10
0
11
0x30 70A2, 0x30 74A2
0
IMASKL
12
0
13
0
MOTOROLA
14
0
16-34
LSB
15
0