MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 359

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3.1 Memory Devices Interface Example
MPC555
USER’S MANUAL
wait states counter has expired, this assertion terminates the memory cycle. When
SETA is cleared, it is forbidden to assert external TA less than two clocks before the
wait states counter expires.
Figure 10-5
static memory device. In this case CSx is connected directly to the chip enable (CE)
of the memory device. The WE/BE[0:3] lines are connected to the respective W in the
memory device where each WE/BE line corresponds to a different data byte.
In
strobes for the transaction are supplied by the OE and the WE/BE lines (if pro-
grammed as WE/BE). Because the ACS bits in the corresponding ORx register = 00,
CS is asserted at the same time that the address lines are valid. Note that because
CSNT is set, the WE signal is negated a quarter of a clock earlier than normal.
Figure
/
MPC556
Figure 10-5 MPC555 / MPC556 GPCM–Memory Devices Interface
10-6, the CSx timing is the same as that of the address lines output. The
MPC555 / MPC556
describes the basic connection between the MPC555 / MPC556 and a
Address
WE/BE
Data
CSx
OE
MEMORY CONTROLLER
Rev. 15 October 2000
Address
CE
OE
W
Data
Memory
MOTOROLA
10-7