MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 381

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Bit(s)
17:19
20:21
24:25
0:16
22
23
26
27
28
29
30
31
/
WEBS
TBDIP
LBDIP
MPC556
Name
SETA
WP
BA
AT
PS
—
—
BI
V
Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being access-
ed by an internal bus master. (The address types are also compared.) These bits are used in
conjunction with the AM[0:16] bits in the OR.
Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note
that the address type field uses only AT[0:2] and does not need AT[3] to define the memory type
space. For a full definition of address types, refer to
Port size
00 = 32-bit port
01 = 8-bit port
10 = 16-bit port
11 = Reserved
Reserved
Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 = Both read and write accesses are allowed
1 = Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
Reserved
Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 = The WE/BE pads operate as WE
1 = The WE/BE pads operate as BE
Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP pin in burst cycles.
Note: it is not allowed to set both LBDIP and TBDIP bits in a region’s base registers; the behavior
of the design in such cases is unpredictable.
0 = Normal timing for BDIP assertion (asserts one clock after negation of TS
1 = Late timing for BDIP assertion (asserts after the programmed number of wait states
External transfer acknowledge
0 = TA generated internally by memory controller
1 = TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
Burst inhibit
0 = Memory controller drives BI negated (high). The bank supports burst accesses.
1 = Memory controller drives BI asserted (low). The bank does not support burst accesses.
Note: Following a system reset, the BI bit is set in OR0.
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set. Note that an access to a region
that has no V-bit set may cause a bus monitor timeout. Note also that following a system reset,
the V-bit in BR0 reflects the value of ID3 in the reset configuration word.
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write
to this memory bank is attempted
have no meaning when this bit is set
Table 10-7 BR0 – BR3 Bit Descriptions
MEMORY CONTROLLER
Rev. 15 October 2000
Description
9.5.7.6 Address
Types.
MOTOROLA
10-29