MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 877

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

F.1 Introduction
MPC555 / MPC556
USER’S MANUAL
NOTES:
RCPU Load/Store
RCPU Instruction
CPUs are active)
Peripheral Mode
(ony ext. master
(both ext. & int.
Table F-1
combinations. The clock values show the number of clocks from the moment an ad-
dress is valid on a specific bus, until data is back on that same bus. The following as-
sumptions were used when compiling the information:
1. “/” comes for on/off page flash access.
2. N is the number of clocks from external address valid till external data valid in the case of read cycle. In the case
3. Assuming BBC is parked on U-BUS.
4. Until address is valid on external pins
Slave Mode
of zero wait states, N = 2.
is active)
Fetches
• The arbitration time was ignored. The values assume that the bus (or buses) in-
• The UIMB works in a mode of 1:1. This is relevant for IMB accesses values. In
• The basic delay of external bus to U-bus is four clocks (external master case).
• All IMB accesses are assumed to be 16-bit accesses only. If 32-bit accesses are
volved in a transaction was in the IDLE state when the transaction needs that bus.
the case of 2:1 mode, the clock latency for a cycle on the IMB should be doubled.
(each IMB access takes two clocks.)
used, then each such IMB access is split into two separate 16-bit cycles with nor-
mal IMB performance for each.
lists all possible memory access timing to internal and external memory
Table F-1 Memory Access Times Using Different Buses
2-1-1-1-1...
FLASH
3/4
4/5
5/6
1
MEMORY ACCESS TIMING
INTERNAL
RAM
MEMORY ACCESS TIMING
3
1
6
7
3
Rev. 15 October 2000
APPENDIX F
IMB
6
7
8
-
SIU
5
6
7
-
External
Memory
Mapped
Internal
EXTERNAL RAM/
4+N
2+N
2
FLASH
mapped
Memory
Internal
Non-
4+N
2+N
Write
SHOW CYCLE
2
-
MOTOROLA
Read
1
2
4
F-1