MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 633

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.4.6 Channel Interrupt Enable Register
CIER — Channel Interrupt Enable Register
17.4.7 Channel Function Select Registers
MPC555
USER’S MANUAL
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10
Bit(s)
Bit(s)
10:15
MSB
0:15
0:4
5:7
8:9
0
0
RESET:
The channel interrupt enable register (CIER) allows the CPU to enable or disable the
ability of individual TPU3 channels to request interrupt service. Setting the appropriate
bit in the register enables a channel to make an interrupt service request; clearing a
bit disables the interrupt.
Encoded 4-bit fields within the channel function select registers specify one of 16 time
functions to be executed on the corresponding channel. Encodings for predefined
functions will be provided in a subsequent draft of this document.
1
0
/
CH[15:0]
MPC556
Name
Name
CIRL
ILBS
—
—
2
0
Reserved
Channel interrupt request level. This three-bit field specifies the interrupt request level for all
channels. This field is used in conjunction with the ILBS field to determine the request level of
TPU3 interrupts.
Interrupt level byte select. This field and the CIRL field determine the level of TPU3 interrupt re-
quests.
00 = IRQ[0:7] selected
01 = IRQ[8:15] selected
10 = IRQ[16:23] selected
11 = IRQ[24:31] selected
Reserved. Note that bits 10:11 represent channel interrupt base vector (CIBV) bits in some TPU3
implementations.
Channel interrupt enable/disable
0 = Channel interrupts disabled
1 = Channel interrupts enabled
Note: The MSB (bit 0 in big-endian mode) represents CH15, and the LSB (bit 15 in big-endian
mode) represents CH0.
3
0
4
0
Table 17-10 CIER Bit Descriptions
Table 17-9 TICR Bit Descriptions
5
0
TIME PROCESSOR UNIT 3
CH 9
Rev. 15 October 2000
6
0
CH 8
7
0
CH 7
8
0
Description
Description
CH 6
9
0
CH 5
10
0
CH 4
11
0
CH 3
12
0
CH 2
13
0
0x30 400A
0x30 440A
MOTOROLA
CH 1
14
0
17-15
CH 0
LSB
15
0