MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 275

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.8 Low-Power Modes
8.8.1 Entering a Low-Power Mode
MPC555
USER’S MANUAL
The LPM and other bits in the PLPRCR are encoded to provide one normal operating
mode and four low-power modes. In normal and doze modes the system can be in
high state with frequency defined by the DFNH bits, or in the low state with frequency
defined by the DFNL bits. The normal-high operating mode is the state out of reset.
This is also the state of the bits after the low-power mode exit signal arrives.
There are four low-power modes:
Low-power modes are enabled by setting the POW bit in the MSR and clearing the
LPML (low-power mode lock) bit in the PLPRCR. Once enabled, a low-power mode is
entered by setting the LPM bits to the appropriate value. This can be done only in one
of the normal modes. The user cannot change the LPM or CSRC bits when the MCU
is in doze mode.
Table 8-6
The default value of the LME bit is determined by MODCK[1:3] during assertion of
the PORESET line. The configuration modes are shown in
• Doze mode
• Sleep mode
• Deep-sleep mode
• Power-down mode
STATE
NOTES:
/
3
MPC556
1. At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state.
2. X = don’t care.
1
2
4
5
6
1
The switching from state three to state four is accomplished by clear-
ing the STBUC and LOCSS bits. If the switching is done when the
PLL is not locked, the system clock will not oscillate until lock condi-
tion is met.
summarizes the control bit descriptions for the different clock power modes.
PORESET
0
1
1
1
1
1
HRESET
Table 8-3 Status of Clock Source
0
0
1
0
1
0
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
LME
0/1
0/1
1
1
1
1
(status)
LOCS
0/1
0/1
x
0
0
0
2
(sticky)
LOCSS
0/1
x
x
0
0
1
2
2
STBUC
0/1
0/1
0
0
0
0
Table
BUCS
1
1
1
0
0
1
8-1.
Oscillator
Oscillator
Source
BUCLK
BUCLK
BUCLK
BUCLK
Clock
Chip
MOTOROLA
8-15