MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 55

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
1.2.11 Two CAN 2.0B Controller Modules (TouCANs)
1.2.12 Queued Serial Multi-Channel Module (QSMCM)
1.3 MPC555 / MPC556 Address Map
MPC555
USER’S MANUAL
Each TouCAN provides these features:
The internal memory map is organized as a single 4-Mbyte block. The user can assign
this block to one of eight locations by programming a register in the USIU. The eight
possible locations are the first eight 4-Mbyte memory blocks starting with address
• Full implementation of CAN protocol specification, version 2.0 A and B
• Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
• Global mask register for message buffers 0 to 13
• Independent mask registers for message buffers 14 and 15
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• 16-bit free-running timer for message time-stamping
• Low power sleep mode with programmable wake-up on bus activity
• Programmable I/O modes
• Maskable interrupts
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture
• Multimaster concept
• High immunity to EMI
• Short latency time for high-priority messages
• Low power sleep mode with programmable wakeup on bus activity
• Queued serial peripheral interface (QSPI)
• Two serial communications interfaces (SCI). Each SCI offers these features:
/
— Provides full-duplex communication port for peripheral expansion or interpro-
— Up to 32 preprogrammed transfers, reducing overhead
— Has 160-byte queue
— Programmable transfer length: from eight to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1)
— Advanced error detection and optional parity generation and detection
— Word length programmable as eight or nine bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins
MPC556
cessor communication
• Wrap-around mode allows continuous sampling of a serial peripheral for effi-
line is detected or a new address byte is received
with discrete inputs
cient interfacing to serial A/D converters
Rev. 15 October 2000
OVERVIEW
MOTOROLA
1-5

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