MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 165

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction
3.14.5 Timebase
3.15 POWERPC Operating Environment Architecture (OEA)
3.15.1 Branch Processor Registers
3.15.1.1 Machine State Register (MSR)
3.15.1.2 Branch Processors Instructions
3.15.2 Fixed-Point Processor
3.15.2.1 Special Purpose Registers
MPC555
USER’S MANUAL
When executing an eieio instruction, the load/store unit will wait until all previous ac-
cesses have terminated before issuing cycles associated with load/store instructions
following the eieio instruction.
A description of the timebase register may be found in
URATION AND PROTECTION
TROL.
The MPC555 / MPC556 has an internal memory space that includes memory-mapped
control registers and internal memory used by various modules on the chip. This mem-
ory is part of the main memory as seen by the MPC555 / MPC556 but cannot be ac-
cessed by any external system master.
The floating-point exception mode encoding in the MPC555 / MPC556 core is as fol-
lows:
The SF bit is reserved set to zero
The IP bit initial state after reset is set as programmed by the reset configuration as
specified by the USIU specification.
The MPC555 / MPC556 implements all the instructions defined for the branch proces-
sor in the UISA in the hardware.
• Unsupported Registers — The following registers are not supported by the
/
MPC555 / MPC556: SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U,
IBAT2L, IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L,
MPC556
Table 3-23 Floating-Point Exception Mode Encoding
Ignore exceptions
Precise
Precise
Precise
Mode
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
and in
SECTION 8 CLOCKS AND POWER CON-
:
FE0
0
0
1
1
SECTION 6 SYSTEM CONFIG-
FE1
0
1
0
1
MOTOROLA
3-43