MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 245

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.5.3 SGPIO Control Register (SGPIOCR)
MPC555
USER’S MANUAL
SGPIOCR — SGPIO Control Register
GDDR
MSB
Bit(s)
Bit(s)
16:23
24:31
22:23
24:31
16
8:15
8:15
0
0
0
0
0:7
0:7
RESET:
RESET:
16
17
18
19
20
21
GDDR
17
/
1
0
1
0
SGPIOA[8:15]
SGPIOC[0:7]
MPC556
SDDRC[0:7]
SGPIOA
SGPIOA
SDDRD
GDDR0
GDDR1
GDDR2
GDDR3
GDDR4
GDDR5
[16:23]
[24:31]
[24:31]
Name
Name
GDDR
—
—
18
2
0
2
0
GDDR
SDDRC[0:7]
19
3
0
3
0
SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the general-
purpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8 dedicated
direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in this group
can be configured separately as general-purpose input or output.
NOTE: Bit 0 controls SGPIOC0, bit 1 controls SGPIOC1, etc.
SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the general-
purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register configures
these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the gener-
al-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register config-
ures these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the gener-
al-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register config-
ures these pins as a group as general-purpose input or output.
SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction
of the corresponding SGPIOC pin zero to seven
Reserved
Group data direction for SGPIOD[0:7]
Group data direction for SGPIOD[8:15]
Group data direction for SGPIOD[16:23]
Group data direction for SGPIOA[8:15]
Group data direction for SGPIOA[16:23]
Group data direction for SGPIOA[24:31]
Reserved
SGPIO data direction for SGPIOD[24:31]. Each SDDRD bit 24:31 controls the direction of
the corresponding SGPIOD pin [24:31].
GDDR
Table 6-22 SGPIODT2 Bit Descriptions
SYSTEM CONFIGURATION AND PROTECTION
Table 6-23 SGPIOCR Bit Descriptions
20
4
0
4
0
GDDR
21
5
0
5
0
Rev. 15 October 2000
RESERVED
22
6
0
0
23
7
0
0
24
8
0
0
Description
Description
25
9
0
0
10
26
0
0
SDDRD[24:31]
RESERVED
11
27
0
0
12
28
0
0
13
29
0
0
0x2F C02C
MOTOROLA
14
30
0
0
LSB
15
31
6-37
0
0