MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 498

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.5.5 Transfer Length
14.7.5.6 Peripheral Chip Selects
MPC555
USER’S MANUAL
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ IMB clock frequen-
cy (204.8 µs with a 40-MHz IMB clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion.
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the IMB clock is op-
erating at a slower rate, the delay between transfers must be increased proportionate-
ly.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive. Re-
served values (from 0b0001 to 0b0111) default to eight bits. The programmed value
must be written into the BITS field in SPCR0. The BITSE bit in each command RAM
byte determines whether the default value (BITSE = 0) or the BITS value (BITSE = 1)
is used.
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in
each command byte. More than one chip-select signal can be asserted at a time, and
more than one external device can be connected to each PCS pin, provided proper
fanout is observed. PCS[0] shares a pin with the slave select SS signal, which initiates
slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a
mode fault occurs.
/
MPC556
where DTL is in the range from one to 255.
QUEUED SERIAL MULTI-CHANNEL MODULE
Standard Delay after Transfer
Rev. 15 October 2000
Delay after Transfer
=
32
----------------------- -
f SYS
¥
DTL
=
-------------
f SYS
17
MOTOROLA
14-36