MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 157

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.11.4 Precise Exceptions
3.11.5 Exception Vector Table
MPC555
USER’S MANUAL
debug port non-maskable interrupt or machine check exception occurs during the ser-
vicing of a previous exception, the machine state information in SRR0 and SRR1 (and,
in some cases, the DAR and DSISR) may not be recoverable; the processor may be
in the process of saving or restoring these registers.
To determine whether the machine state is recoverable, the user can read the RI (re-
coverable exception) bit in SRR1. During exception processing, the RI bit in the MSR
is copied to SRR1 and then cleared. The operating system should set the RI bit in the
MSR at the end of each exception handler’s prologue (after saving the program state)
and clear the bit at the start of each exception handler’s epilogue (before restoring the
program state). Then, if an unordered exception occurs during the servicing of an ex-
ception handler, the RI bit in SRR1 will contain the correct value.
In the MPC555 / MPC556, all synchronous (instruction-caused) exceptions are pre-
cise. When a precise exception occurs, the processor backs the machine up to the in-
struction causing the exception. This ensures that the machine is in its correct
architecturally-defined state. The following conditions exist at the point a precise ex-
ception occurs:
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are
vectored. If the bit is cleared, the exception vector table begins at the physical address
0x0000 0000; if IP is set, the exception vector table begins at the physical address
0xFFF0 0000.
the exception handler routine for each exception type.
1. Architecturally, no instruction following the faulting instruction in the code
2. All instructions preceding the faulting instruction appear to have completed with
3. SRR0 addresses either the instruction causing the exception or the immediate-
4. Depending on the type of exception, the instruction causing the exception may
/
MPC556
stream has begun execution.
respect to the executing processor.
ly following instruction. Which instruction is addressed can be determined from
the exception type and the status bits.
not have begun execution, may have partially completed, or may have complet-
ed execution.
In the MPC555 / MPC556, the exception table can additionally be re-
located by the BBC module to internal memory and reduce the total
size required by the exception table (see
cation).
Table 3-21
shows the exception vector offset of the first instruction of
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
NOTE
4.5 Exception Table Relo-
MOTOROLA
3-35