MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 565

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
Bit(s)
8:15
POL
6:7
0
1
2
3
4
5
0
0
0
1
1
1
Control Bits
/
MPC556
Name
FREN
TRSP
DDR
POL
EN
PIN
EN
CP
0
0
1
0
0
1
—
Table 15-24 PWMSM Output Pin Polarity Selection
Pin input status. The PIN bit reflects the state present on the MPWMSM pin. The software can
thus monitor the signal on the pin.
The PIN bit is a read-only bit. Writing to the PIN bit has no effect.
Data direction register. The DDR bit indicates the direction for the pin when the PWM function
is not used (disable mode). Note that when the PWM function is used, the DDR bit has no effect.
Table 15-24
direction register (DDR) bit.
0 = Pin is an input.
1 = Pin is an output.
Freeze enable. This active high read/write control bit enables the MPWMSM to recognize the
freeze signal on the MIOB.
0 = MPWMSM not frozen even if the MIOB freeze line is active.
1 = MPWMSM frozen if the MIOB freeze line is active.
Transparent mode. The TRSP bit indicates that the MPWMSM double buffers are transparent:
when the software writes to either the MPWMA or MPWMB1 register the value written is imme-
diately transferred to respectively the counter or register MPWMB2.
0 = Transparent mode de-activated.
1 = Transparent mode activated.
Output polarity control. The POL bit works in conjunction with the EN bit and controls whether
the MPWMSM drives the pin with the true or the inverted value of the output flip-flop
Table 15-24
direction register (DDR) bit.
Enable PWM signal generation. The EN bit defines whether the MPWMSM generates a PWM
signal or is used as an I/O channel:
Table 15-24
direction register (DDR) bit.
0 = PWM generation disabled (pin can be used as I/O).
1 = PWM generation enabled (pin is output only).
Reserved
Clock Prescaler. This 8-bit read/write register stores the two’s complement of the desired mod-
ulus value for loading into the built-in 8-bit clock prescaler. The value loaded defines the divide
ratio for the signal that clocks the MPWMSM period counter.
ratio according to the CP values.
DDR
—
—
0
1
0
1
Table 15-23 MPWMSMSCR Bit Descriptions
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Pin Direction
lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
(I/O)
O
O
O
O
I
I
Rev. 15 October 2000
Always High
Always Low
High Pulse
Low Pulse
Pin State
Input
Input
Description
Falling Edge
Rising Edge
Periodic
Edge
—
—
—
—
Table 15-15
Falling Edge
Rising Edge
Variable
Edge
—
—
—
—
gives the clock divide
Interrupt On
Falling Edge
Rising Edge
MOTOROLA
Optional
—
—
—
—
15-29