MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 506

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.8.1 SCI Registers
MPC555
USER’S MANUAL
The SCI programming model includes the QSMCM global and pin control registers
and the DSCI registers.
The DSCI registers, listed in
registers, and 34 data registers. All registers may be read or written at any time by the
CPU. Rewriting the same value to any DSCI register does not disrupt operation; how-
ever, writing a different value into a DSCI register when the DSCI is running may dis-
rupt operation. To change register values, the receiver and transmitter should be
disabled with the transmitter allowed to finish first. The status flags in register SCxSR
*Reads access the RDRx; writes access the TDRx.
During SCIx initialization, two bits in the SCCxR1 should be written last: the transmitter
enable (TE) and receiver enable (RE) bits, which enable SCIx. Registers SCCxR0 and
SCCxR1 should both be initialized at the same time or before TE and RE are asserted.
A single half-word write to SCCxR1 can be used to initialize SCIx and enable the trans-
mitter and receiver.
can be cleared at any time.
/
MPC556
(non-queue mode only)
0x30 502C — 0x30
0x30 504C-6A
0x30 500C
0x30 500A
0x30 500E
0x30 502A
0x30 5008
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
Address
504A
QUEUED SERIAL MULTI-CHANNEL MODULE
QSCI1 Transmit Queue
QSCI1 Receive Queue
Table 14-22 SCI Registers
Table
Memory Area
Memory Area
QSCI1CR
QSCI1SR
SCC1R0
SCC1R1
SCC2R0
SCC2R1
Rev. 15 October 2000
SC1DR
SC2DR
SC1SR
SC2SR
Name
14-22, consist of five control registers, three status
SCI1 Control Register 0
See
SCI1 Control Register 1
See
SCI1 Status Register
See
SCI1 Data Register
Transmit Data Register (TDR1)*
Receive Data Register (RDR1)*
See
SCI2 Control Register 0
SCI2 Control Register 1
SCI2 Status Register
SCI2 Data Register
Transmit Data Register (TDR2)*
Receive Data Register (RDR2)*
QSCI1 Control Register
Interrupts, wrap, queue size and enables
for receive and transmit, QTPNT.
See
QSCI1 Status Register
OverRun error flag, queue status flags,
QRPNT, and QPEND.
See
QSCI1 Transmit Queue Data locations (on
half-word boundary)
QSCI1 Receive Queue Data locations (on
half-word boundary)
Table 14-23
Table 14-24
Table 14-25
Table 14-26
Table 14-30
Table 14-31
Usage
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
MOTOROLA
14-44