MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 709

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.3.1.1 Restrictions
21.3.1.2 Byte and Half-Word Working Modes
MPC555
USER’S MANUAL
There are cases when the same watchpoint can be detected more than once during
the execution of a single instruction, e.g. a load/store watchpoint is detected on more
than one transfer when executing a load/store multiple/string or a load/store watch-
point is detected on more than one byte when working in byte mode. In all these cases
only one watchpoint of the same type is reported for a single instruction. Similarly, only
one watchpoint of the same type can be counted in the counters for a single instruc-
tion.
Since watchpoint events are reported upon the retirement of the instruction that
caused the event, and more than one instruction can retire from the machine in one
clock, consequent events may be reported in the same clock. Moreover the same
event, if detected on more than one instruction (e.g., tight loops, range detection), in
some cases will be reported only once. Note that the internal counters count correctly
in these cases.
Do not put a breakpoint on an mtspr ICTRL instruction. When a breakpoint is set on
an mtspr ICTRL Rx instruction and the value of bit 28 (IFM) is one, the result will be
unpredictable. A breakpoint can be taken or not on the instruction and the value of the
IFM bit can be either zero or one. Also, do not put a breakpoint on an mtspr ICTRL Rx
instruction when Rx contains one in bit 28.
The CPU watchpoints and breakpoints support enables the user to detect matches on
bytes and half-words even when accessed using a load/store instruction of larger data
widths, for example when loading a table of bytes using a series of load word instruc-
tions. In order to use this feature, the user needs to program the byte mask for each
of the L-data comparators and to write the needed match value to the correct half-word
of the data comparator when working in half-word mode and to the correct bytes of the
data comparator when working in byte mode.
Since bytes and half-words can be accessed using a larger data width instruction, it is
impossible for the user to predict the exact value of the L-address lines when the re-
quested byte/half-word is accessed, (e.g., if the matched byte is byte two of the word
and it is accessed using a load word instruction), the L-address value will be of the
word (byte zero). Therefore, the CPU masks the two least-significant bits of the L-ad-
dress comparators whenever a word access is performed and the least-significant bit
whenever a half-word access is performed.
Address range is supported only when aligned according to the access size. (See ex-
amples)
• Both “go to x” and “continue” working modes are supported for the instruction
/
breakpoints.
MPC556
DEVELOPMENT SUPPORT
Rev. 15 October 2000
MOTOROLA
21-13