MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 679

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

19.7 Voltage Control for Programming and Erasing
19.7.1 Pulse Status
19.7.2 Pulse Width Timing Equation
MPC555
USER’S MANUAL
during the erase margin read while the shadow information is read. For the erase op-
eration to be completed, block zero must also be fully verified.
Bits for controlling the voltage during programming and erasing are found in the CM-
FCTL register.
During a program or erase pulse, the HVS bit is set while the pulse is active or during
recovery. The BIU does not acknowledge an access to an array location if HVS = 1.
While HVS = 1, SES cannot be changed. The program or erase pulse becomes active
by setting the EHV bit and is terminated by clearing EHV or by the pulse width timing
control.
The recovery time is the time required for the CMF EEPROM to remove the program
or erase voltage from the array or shadow information before switching to another
mode of operation. The recovery time is determined by the system clock range
(SCLKR[0:2]) and the PE bit. If SCLKR = 000, the recovery time is 128 clocks. Other-
wise, the recovery time is 48 periods of the scaled clock.
Once reset is completed HVS will indicate no program or erase pulse (HVS = 0).
To control the pulse widths for program and erase operations, the CMF EEPROM uses
the system clock and the timing control in CMFCTL. The total pulse time is defined by
the following pulse width equation:
EHV
HVS
/
MPC556
Setting the SIE bit disables normal array access. SIE should be
cleared after verifying the shadow information.
Recovery = 48 Scaled Clocks or 128 Clocks
Figure 19-5 Pulse Status Timing
CDR MoneT FLASH EEPROM
Rev. 15 October 2000
NOTE
Pulse Width
Recovery
MOTOROLA
19-27