MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 226

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.11 Freeze Operation
6.12 Low Power Stop Operation
6.13 System Configuration and Protection Registers
MPC555
USER’S MANUAL
Clock
System
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic
interrupt timer, the real-time clock, the time base counter, and the decrementer can be
disabled. This is controlled by the associated bits in the control register of each timer.
If programmed to stop during FREEZE assertion, the counters maintain their values
while FREEZE is asserted, unless changed by the software. The bus monitor, howev-
er, remains enabled regardless of this signal.
When the processor is set in a low-power mode (doze, sleep, or deep sleep), the soft-
ware watchdog timer is frozen. It remains frozen and maintain its count value until the
processor exits this state and resumes executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these low-
power modes. They continue to run at their respective frequencies. These timers are
capable of generating an interrupt to bring the MCU out of these low-power modes.
This section provides diagrams and bit descriptions of the system configuration and
protection registers.
/
MPC556
(SYPCR)
FREEZE
Disable
SWE
Clock
SYSTEM CONFIGURATION AND PROTECTION
Figure 6-9 SWT Block Diagram
Divide By
2048
Service
SWSR
Logic
Rev. 15 October 2000
(SYPCR)
MUX
SWP
Reload
SWR / Decrementer
Rollover = 0
SWTC
16-bit
Time-out
MOTOROLA
or NMI
Reset
6-18