MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 394

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.6.3 Reserved Location (Bus) and Possible Actions
MPC555
USER’S MANUAL
If the storage reservation is lost, it is guaranteed that a store-with-reservation request
by the CPU will not modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved lo-
cation on the U-bus has been touched by another master. The L2U drives the reser-
vation status back to the core.
When the reserved location in the SRAM on the L-bus is touched by an alternate mas-
ter, on the following clock, the L2U indicates to the CPU that the reservation has been
touched. On assertion of the cancel-reservation signal, the RCPU clears the internal
reservation bit. If an stwcx cycle has been issued at the same time, the RCPU aborts
the cycle.
Storage reservation is set regardless of the termination status (address or data phase)
of the lwarx access. Storage reservation is cleared regardless of the data phase ter-
mination status of the stwcx access if the address phase is terminated normally.
Storage reservation will be cleared regardless of the data phase termination status of
the write requests by another master to the reserved address if the address phase of
the write access is terminated normally on the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx
instruction, the reservation is not guaranteed.
Once the CPU core reserves a memory location, the L2U module is responsible for
snooping L-bus and U-bus for possible intrusion of the reserved location. Under cer-
tain circumstances, the L2U depends on the USIU or the UIMB to provide status of res-
ervation on external bus and the IMB3 respectively.
Table 11-2
/
MPC556
lists all reservation protocol cases supported by the L2U snooping logic.
L-BUS TO U-BUS INTERFACE (L2U)
Rev. 15 October 2000
MOTOROLA
11-8