MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 146

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DEC — Decrementer Register
SRR0 — Machine Status Save/Restore Register 0
MSB
MSB
3.9.6 Machine Status Save/Restore Register 0 (SRR0)
3.9.7 Machine Status Save/Restore Register 1 (SRR1)
MPC555
USER’S MANUAL
0
0
clock in the MPC555 / MPC556, refer to
MPC555 / MPC556 Internal Clock
ister
The DEC does not run after power-up and must be enabled by setting the TBE bit in
the TBSCR register, see
register. A decrementer exception may be signaled to software prior to initialization.
The machine status save/restore register 0 (SRR0) is a 32-bit register that identifies
where instruction execution should resume when an rfi instruction is executed follow-
ing an exception. It also holds the effective address of the instruction that follows the
System Call (sc) instruction.
When an exception occurs, SRR0 is set to point to an instruction such that all prior in-
structions have completed execution and no subsequent instruction has begun execu-
tion. The instruction addressed by SRR0 may not have completed execution,
depending on the exception type. SRR0 addresses either the instruction causing the
exception or the immediately following instruction. The instruction addressed can be
determined from the exception type and status bits.
When an exception occurs, SRR0 is set to point to an instruction such that all prior in-
structions have completed execution and no subsequent instruction has begun execu-
tion. The instruction addressed by SRR0 may not have completed execution,
depending on the exception type. SRR0 addresses either the instruction causing the
exception or the immediately following instruction. The instruction addressed can be
determined from the exception type and status bits.
SRR1 is a 32-bit register used to save machine status on exceptions and to restore
machine status when an rfi instruction is executed.
1
1
2
2
/
(SCCR).
3
3
MPC556
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Table
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
6-16. Power-on reset stops its counting and clears the
RESET: UNCHANGED
Decrementing Counter
RESET: UNDEFINED
Signals, and
SRR0
6.6 MPC555 / MPC556
8.12.1 System Clock Control Reg-
Decrementer,
MOTOROLA
SPR 22
SPR 26
3-24
8.6
LSB
LSB
31
31