MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 251

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.4 Reset Status Register
MPC555
USER’S MANUAL
RSR — Reset Status Register
EHRS ESRS LLRS SWRS CSRS
Bit(s)
MSB
0
0
0
1
2
3
4
5
6
7
8
RESET:
All of the reset sources are fed into the reset controller. The 16-bit reset status register
(RSR) reflects the most recent source, or sources, of reset. (Simultaneous reset re-
quests can cause more than one bit to be set at the same time.) This register contains
one bit for each reset source. A bit set to logic one indicates the type of reset that oc-
curred.
Once set, individual bits in the RSR remain set until software clears them. Can be
cleared by writing a one to the bit. A write of zero has no effect on the bit. The register
can be read at all times. The reset status register receives its default reset values dur-
ing power-on reset. The RSR is powered by the KAPWR pin.
/
1
0
DBHRS
DBSRS
EHRS
ESRS
SWRS
OCCS
MPC556
Name
CSRS
LLRS
JTRS
2
0
1
1
External hard reset status
0 = No external hard reset has occurred
1 = An external hard reset has occurred
External soft reset status
0 = No external soft reset has occurred
1 = An external soft reset has occurred
Loss of lock reset status
0 = No enabled loss-of-lock reset has occurred
1 = An enabled loss-of-lock reset has occurred
Software watchdog reset status
0 = No software watchdog reset has occurred
1 = A software watchdog reset has occurred
Checkstop reset status
0 = No enabled checkstop reset has occurred
1 = An enabled checkstop reset has occurred
Debug port hard reset status
0 = No debug port hard reset request has occurred
1 = A debug port hard reset request has occurred
Debug port soft reset status
0 = No debug port soft reset request has occurred
1 = A debug port soft reset request has occurred
JTAG reset status
0 = No JTAG reset has occurred
1 = A JTAG reset has occurred
On-chip clock switch
0 = No on-chip clock switch reset has occurred
1 = An on-chip clock switch reset has occurred
Table 7-3 Reset Status Register Bit Descriptions
3
0
4
0
HRS
DB-
5
0
Rev. 15 October 2000
SRS
DB-
6
0
JTRS OCCS
7
0
RESET
8
0
Description
ILBC
9
0
GPOR
10
1
RST
GH-
11
1
GSRS
12
T
1
13
0
RESERVED
0x2F C288
MOTOROLA
14
0
15
0
7-5