MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 410

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

12.5.2 Test control register (UTSTCREG)
12.5.3 Pending Interrupt Request Register (UIPEND)
MPC555
USER’S MANUAL
UIPEND — Pending Interrupt Request Register
LVL16
Bit(s)
LVL0
MSB
4:31
1:2
16
HRESET:
HRESET:
0
0
0
0
3
The UTSTCREG register is used for factory testing only.
The UIPEND register is a read-only status register which reflects the state of the 32
interrupt levels. The state of the IRQ0 is shown in bit 0, the state of IRQ1 is shown in
bit 1 and so on. This register is accessible only in supervisor mode.
LVL1
IRQ17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31
/
HSPEED
1
0
17
IRQMUX
0
MPC556
Name
STOP
—
LVL2
2
0
18
0
Stop enable.
0 = Enable system clock for IMB bus
1 = Disable IMB system clock
To avoid complications at restart and data corruption, system software must stop each slave on
the IMB before setting the STOP bit. Software must also ensure that all IMB interrupts have been
serviced before setting this bit.
Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt re-
quests onto the eight IMB interrupt request lines.
00 = Disables the multiplexing scheme on the interrupt controller within this interface. What this
01 = Enables the IMB IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of
10 = Enables the IMB IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of
11 = Enables the IMB IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of
Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the
U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of
times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1
will have no effect.
0 = IMB frequency is the same as that of the U-bus
1 = IMB frequency is one half that of the U-bus
Reserved
LVL3
3
0
19
0
means is that the IMB IRQ [0:7] signals are non-multiplexed, only providing 8 (0-7) interrupt
request lines to the interrupt controller
16 (0-15) interrupt sources
24 (0-23) interrupt sources
32 (0-31) interrupt sources
LVL4
4
0
20
0
Table 12-6 UMCR Bit Descriptions
U-BUS TO IMB3 BUS INTERFACE (UIMB)
LVL5
5
0
21
0
LVL6
Rev. 15 October 2000
6
0
22
0
LVL7
7
0
23
0
LVL8
8
0
24
0
Description
LVL9
9
0
25
0
LVL0 LVL11 LVL12 LVL13 LVL14 LVL15
10
0
26
0
11
0
27
0
12
0
28
0
13
0
29
0
0x30 7FA0
MOTOROLA
14
0
30
0
LSB
15
12-8
0
31
0