MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 601

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.6 Interrupts
MPC555
USER’S MANUAL
The TouCAN can generate one interrupt level on the IMB. This level is programmed
into the priority level bits in the interrupt configuration register (CANICR). This value
determines which interrupt signal is driven onto the bus when an interrupt is requested.
Each one of the 16 message buffers can be an interrupt source, if its corresponding
IMASK bit is set. There is no distinction between transmit and receive interrupts for a
particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG
bit is set when the corresponding buffer completes a successful transmission/recep-
tion. An IFLAG bit is cleared when the CPU reads IFLAG while the associated bit is
set, and then writes it back as zero (and no new event of the same type occurs be-
tween the read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and
have flag bits located in the error and status register (ESTAT). The bus off and error
interrupt mask bits (BOFFMSK and ERRMSK) are located in CANCTRL0, and the
wake up interrupt mask bit (WAKEMSK) is located in the module configuration regis-
ter. Refer to
The TouCAN module is capable of generating one of the 32 possible interrupt levels
on the IMB3. The 32 interrupt levels are time multiplexed on the IMB3 IRQ[0:7] lines.
All interrupt sources place their asserted level on a time multiplexed bus during four
different time slots, with eight levels communicated per slot. The ILBS[0:1] signals in-
dicate which group of eight are being driven on the interrupt request lines.
The level that the TouCAN will drive onto IRQ[7:0] is programmed in the three interrupt
request level (IRL) bits located in the interrupt configuration register. The two ILBS bits
in the ICR register determine on which slot the TouCAN should drive its interrupt sig-
nal. Under the control of ILBS, each interrupt request level is driven during the time
multiplexed bus during one of four different time slots, with eight levels communicated
per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than
one source on a module requests an interrupt at the same level, the system software
must assign a priority to each source requesting at that level.
interrupt levels on IRQ with ILBS.
/
MPC556
16.7 Programmer’s Model
CAN 2.0B CONTROLLER MODULE
Table 16-9 Interrupt Levels
ILBS[0:1]
Rev. 15 October 2000
00
01
10
11
for more information on these registers.
Levels
16:23
24:31
8:15
0:7
Figure 16-5
displays the
MOTOROLA
16-19