MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 87

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.4.2 Pad Module Configuration Register (PDMCR)
MPC555
USER’S MANUAL
PDMCR
SLRC0
HARD RESET:
HARD RESET:
Bit(s)
4:5
16
0
0
0
0
1
2
3
6
0 = 3-V bus pins full drive (50-pF load)*
1 = 3-V bus pins reduced drive (25-pF load)
* The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register
The slew rate and weak pull-up/pull-down characteristics of some pins are controlled
by bits in the PDMCR. This register resides in the SIU memory map. The contents of
the PDMCR are illustrated below. The PORESET signal resets all the PDMCR bits
asynchronously.
NOTE:
1. FTPU_PU is only available on mask set K62N and later.
(for the TPU, QADC, USIU (SGPIO), QSPI, TouCAN, QSCI, and MIOS pins).
SLRC
17
/
1
1
0
0
SLRC0
SLRC1
SLRC2
SLRC3
– Pad Module Configuration Register
MPC556
Name
PRDS
—
SLRC
18
2
2
0
0
SLRC0 controls the slew rate of the following modules: TPU, QADC, USIU (SGPIO).
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
SLRC1 controls the slew rate of the QSPI and TouCAN modules.
0 = Slow slew rate for pins. Controls slew rate pins of 50 ns.
1 = Normal slew rate for pins
SLRC2 controls the slew rate of the QSCI module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
SLRC3 controls the slew rate of the MIOS module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
Reserved
The PRDS bit is used to enable or disable the weak pull-up/pull-down devices in the pads related
to SGPIO and all pads related to IMB modules.
PRDS.
0 = Enable pull-up/pull-down devices
1 = Disable pull-up/pull-down devices
SLRC
19
3
3
0
0
20
4
Reserved
0
0
Table 2-3 PDMCR Bit Descriptions
21
5
0
0
SIGNAL DESCRIPTIONS
PRDS
Rev. 15 October 2000
22
6
0
0
SPRD
RESERVED
23
S
7
0
0
.
.
FTPU
_PU
24
0
8
0
Description
1
25
0
9
0
Table 2-4
10
26
0
0
illustrates which pins are affected by
27
11
0
0
Reserved
28
12
0
0
13
29
0
0
0x2F C03C
MOTOROLA
30
14
0
0
31
15
2-29
0
0