MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 266

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.4 System Clock During PLL Loss of Lock
8.5 Low-Power Divider
MPC555
USER’S MANUAL
Where MF = the value stored on MF[0:11]. This is one less than the desired frequency multiplication factor.
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external
clock source is generating the system clock. In this case, if loss of lock is detected and
the LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock
source continues to function as the PLL’s output clock. The USIU timers can operate
with the input clock to the PLL, so that these timers are not affected by the PLL loss of
lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MCU can switch to the backup clock by
setting the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode
enable (LME) bit in the SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example,
if LOLRE is set) disables the PLL output clock until the lock condition is met. During
hard reset, the STBUC bit is set as long as the PLL lock condition is not met and clears
when the PLL is locked. If STBUC and LME are both set, the system clock switches to
the backup clock, and the chip operates in limp mode until STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK
is sent to a low-power divider block.) This block generates all other clocks in normal
operation, but has the ability to divide the output frequency of the VCO before it gen-
erates the general system clocks sent to the rest of the MPC555 / MPC556. The PLL
System Frequency (FREQ
The purpose of the low-power divider block is to allow the user to reduce and restore
the operating frequencies of different sections of the MPC555 / MPC556 without losing
the PLL lock. Using the low-power divider block, the user can still obtain full chip op-
eration, but at a lower frequency. This is called gear mode. The selection and speed
of gear mode can be changed at any time, with changes occurring immediately.
The low-power divider block is controlled in the system clock control register (SCCR).
The default state of the low-power divider is to divide all clocks by one. Thus, for a 40-
MHz system, the general system clocks are each 40 MHz.
/
0 < MF + 1 < 4
MF + 1 ≥ 4
MPC556
When the VCO is the system clock source, chip operation is unpre-
dictable while the PLL is unlocked. Note further that a switch to the
backup clock is possible only if the LME bit in the SCCR is set.
CLOCKS AND POWER CONTROL
SYS
) is always divided by at least 2.
(680 x (MF + 1) – 120) pF
1100 x (MF + 1) pF
Rev. 15 October 2000
NOTE
MOTOROLA
8-6