MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 269

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.6.1 General System Clocks
MPC555
USER’S MANUAL
MODCK[1:3]
NOTES:
1. For other implementations in the MPC500 family, MODCK2 could be inverted.
The values of the PITRTCLK clock division and TMBCLK clock division can be
changed by software. The RTDIV bit value in the SCCR register defines the division
of PITRTCLK. All possible combinations of the TMBCLK divisions are listed in
8-2.
The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and
GCLK2_50) are the basic clock supplied to all modules and sub-modules on the
MPC555 / MPC556. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC.
GCLK1C and GCLK2C are stopped when the chip enters the doze-low power mode.
GCLK1 and GCLK2 are supplied to the SIU and the clock module. The external bus
clock GCLK2_50 is the same as CLKOUT. The general system clock defaults to VCO/
000
001
010
011
100
101
110
111
/
MPC556
1
The reset value of the PLL pre-divider is 1.
LME
0
0
1
1
0
0
1
Table 8-1 Reset Clocks Source Configuration
MF + 1
Default Values @ PORESET
513
1
5
1
1
5
1
SCCR[TBS]
Table 8-2 TMBCLK Divisions
CLOCKS AND POWER CONTROL
1
0
0
Division
PITCLK
256
256
256
256
256
256
4
Rev. 15 October 2000
TMBCLK
Division
MF + 1
1, 2
> 2
16
16
16
16
—
4
4
4
NOTE
Used for testing purposes.
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 20 MHz.
Limp mode disabled.
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 4 MHz.
Limp mode enabled.
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 20 MHz.
Limp mode enabled.
Normal operation, PLL enabled. 1:1 Mode
freqclkout(max) = freq(EXTCLK)
Limp mode disabled.
Normal operation, PLL enabled.
Main timing reference is freq(EXTCLK) = 3-5 MHz.
Limp mode disabled.
Normal operation, PLL enabled. 1:1 Mode
freqclkout(max) = freq(EXTCLK)
Limp mode enabled.
TMBCLK
Division
16
16
4
SPLL Options
MOTOROLA
Table
8-9