MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 644

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18.2 DPTRAM Configuration and Block Diagram
18.3 Programming Model
MPC555
USER’S MANUAL
The DPTRAM module consists of two separately addressable sections. The first is a
set of memory-mapped control and status registers used for configuration (DPTMCR,
RAMBAR, MISRH, MISRL, MISCNT) and testing (DPTTCR) of the DPTRAM array.
The second section is the array itself.
All DPTRAM module control and status registers are located in supervisor data space.
User reads or writes of these will result in a bus error.
When the TPU3 is using the RAM array for microcode control store, none of these con-
trol registers have any effect on the operation of the RAM array.
All addresses within the 64-byte control block will respond when accessed properly.
Unimplemented addresses will return zeros for read accesses. Likewise, unimple-
mented bits within registers will return zero when read and will not be affected by write
operations.
Table 18-1
are offsets from the base address for the module. Refer to
• Includes built in check logic which scans the array contents and calculates the
• IMB3 bus interface
• Two TPU3 interface units
• Bytes, half-word or word accessible
/
RAM signature
MPC556
shows the DPTRAM control and status registers. The addresses shown
RAM Mode
RAM
TPU
TPU
Figure 18-1 DPTRAM Configuration
DUAL-PORT TPU RAM (DPTRAM)
Rev. 15 October 2000
TPU Microcode Mode
1.3 MPC555 / MPC556 Ad-
RAM
TPU
TPU
Local Bus
Local Bus
MOTOROLA
18-2