MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 750

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
ECR — Exception Cause Register
Bit(s)
11:12
22:27
16
4:5
10
13
14
15
16
17
18
19
20
21
0
0
0
0
0
0
1
2
3
6
7
8
9
RESET:
RESET:
SEE
RST
17
0
/
1
0
DTLBER
ITLBER
CHSTP
FPUVE
FPASE
Name
DECE
MPC556
SYSE
MCE
EXTI
PRE
RST
SEE
ALE
TR
—
—
—
—
—
—
—
CHST
SERV
RE-
ED
18
P
2
0
0
Reserved
Reset interrupt bit. This bit is set when the system reset pin is asserted.
Checkstop bit. Set when the processor enters checkstop state.
Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
Reserved
External interrupt bit. Set when the external interrupt is asserted.
Alignment exception bit. Set when the alignment exception is asserted.
Program exception bit. Set when the program exception is asserted.
Floating point unavailable exception bit. Set when the program exception is asserted.
Decrementer exception bit. Set when the decrementer exception is asserted.
Reserved
System call exception bit. Set when the system call exception is asserted.
Trace exception bit. Set when in single-step mode or when in branch trace mode.
Floating point assist exception bit. Set when the floating point assist exception occurs.
Reserved
Software emulation exception. Set when the software emulation exception is asserted.
Reserved
Implementation specific instruction protection error
This bit is set as a result of an instruction protection error. Results in debug mode entry if debug
mode is enabled and the corresponding enable bit is set.
Reserved
Implementation specific data protection error
This bit is set as a result of an data protection error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
Reserved
MCE
BER
ITL-
19
3
0
0
SERV
RESERVED
RE-
ED
20
4
0
0
Table 21-27 ECR Bit Descriptions
DTL-
BER
21
5
0
0
DEVELOPMENT SUPPORT
EXTI
Rev. 15 October 2000
22
6
0
0
ALE
23
7
0
0
PRE
RESERVED
24
8
0
0
Description
FPUV
25
9
E
0
0
DECE
10
26
0
0
RESERVED
11
27
0
0
LBRK
12
28
0
0
SYSE
IBRK
13
29
0
0
MOTOROLA
EBRK
SPR 148
TR
14
30
0
D
0
FPAS
21-54
DPI
15
31
E
0
0