MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 539

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.2 Submodule Numbering, Naming and Addressing
15.3 MIOS1 Signals
MPC555
USER’S MANUAL
A block is a group of four 16-bit registers. Each of the blocks within the MIOS1 ad-
dressing range is assigned a block number. The first block is located at the base ad-
dress of the MIOS1. The blocks are numbered sequentially starting from 0.
Every submodule instantiation is also assigned a number. The number of a given sub-
module is the block number of the first block of this submodule.
A submodule is assigned a name made of its acronym followed by its submodule num-
ber. For example, if submodule number 18 were an MPWMSM, it would be named
MPWMSM18.
This numbering convention does not apply to the MBISM, the MCPSM and the
MIRSMs. The MBISM and the MCPSM are unique in the MIOS1 and do not need a
number. The MIRSMs are numbered incrementally starting from zero.
The MIOS1 base address is defined at the chip level and is referred to as the “MIOS1
base address.” The MIOS1 addressable range is four Kbytes.
The base address of a given implemented submodule within the MIOS1 is the sum of
the base address of the MIOS1 and the submodule number multiplied by eight. (Refer
to
This does not apply to the MBISM, the MCPSM and the MIRSMs. For these submod-
ules, refer to the MIOS1 memory map
The MIOS1 requires 34 pins: 10 MDASM pins, eight MPWMSM pins and 16 MPIOSM
pins. The usage of these pins is shown in the block diagram of
configuration description of
MDA, MPWMSM pins have a prefix of MPWM and the port pins have a prefix of MPIO.
The modulus counter clock and load pins are multiplexed with MDASM pins.
The MIOS1 input and output pin names are composed of five fields according to the
following convention:
Table
• MIOS 16-bit parallel port I/O submodule (MPIOSM):
• “M”
• <submodule short_prefix>
• <submodule number>
• <pin attribute suffix> (optional)
• <bit number> (optional)
/
— Software selectable output pulse polarity
— Software readable output pin status
— Possible use of pin as I/O port when PWM function is not needed
— 16 parallel input/output pins
— Simple data direction register (DDR) concept for selection of pin direction
MPC556
15-36.)
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Table
Rev. 15 October 2000
15-36. In the figure, MDASM pins have a prefix
(Figure
15-2).
Figure 15-1
MOTOROLA
and in the
15-3