MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 574

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MIOS1RPR1 — MIRSM1 Request Pending Register
15.15 MIOS1 Function Examples
15.15.1 MIOS1 Input Double Edge Pulse Width Measurement
MPC555
USER’S MANUAL
IRP31 IRP30 IRP29 IRP28 IRP27
MSB
0
0
RESET:
The versatility of the MIOS1 timer architecture is based on multiple counters and cap-
ture/compare channel units interconnected on 16-bit counter buses. This section in-
cludes some typical application examples to show how the submodules can be
interconnected to form timing functions. The diagrams used to illustrate these exam-
ples show only the blocks utilized for that function.
To illustrate the timing range of the MIOS1 in different applications, many of the follow-
ing paragraphs include time intervals quoted in microseconds and seconds. The as-
sumptions used are that f
cycle) and with the maximum overall prescaling (32 µs cycle). For other f
cle rates and prescaler choices, the times mentioned in these paragraphs scale appro-
priately.
To measure the width of an input pulse, the MIOS double action submodule (MDASM)
has two capture registers so that only one interrupt is needed after the second edge.
The software can read both edge samples and subtract them to get the pulse width.
The leading edge sample is double latched so that the software has the time of one
full period of the input signal to read the samples to be sure that nothing is lost. De-
pending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be mea-
sured. Note that a software option is provided to also generate an interrupt after the
first edge.
1
0
/
MPC556
2
0
Bit(s)
10:11
5:8
12
13
14
15
0
1
2
3
4
9
3
0
Table 15-35 MIOS1RPR1 Bit Descriptions
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
4
0
Name
IRP31
IRP30
IRP29
IRP28
IRP27
IRP22
IRP19
IRP18
IRP17
IRP16
—
—
5
0
SYS
MDASM31 IRQ pending bit
MDASM30 IRQ pending bit
MDASM29 IRQ pending bit
MDASM28 IRQ pending bit
MDASM27 IRQ pending bit
Reserved
MMCSM22 IRQ pending bit
Reserved
MPWMSM19 IRQ pending bit
MPWMSM18 IRQ pending bit
MPWMSM17 IRQ pending bit
MPWMSM16 IRQ pending bit
RESERVED
is at 40 MHz with minimum overall prescaling (50 ns
Rev. 15 October 2000
6
0
7
0
8
0
Description
IRP22
9
0
RESERVED
10
0
11
0
IRP19 IRP18 IRP17 IRP16
12
0
13
0
SYS
0x30 6C46
MOTOROLA
14
clock cy-
0
15-38
LSB
15
0