MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 209

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555 / MPC556
USER’S MANUAL
The MPC555 / MPC556 incorporates many system functions that normally must be
provided in external circuits. In addition, it is designed to provide maximum system
safeguards again hardware and/or software faults. The system configuration and pro-
tection sub-module provides the following features:
• System Configuration — The USIU allows the user to configure the system ac-
• Interrupt Configuration — The interrupt controller receives interrupt requests
• General-Purpose I/O — The USIU provides 64 pins for general-purpose I/O. The
• External Master Modes Support — External master modes are special modes
• Bus Monitor — The SIU provides a bus monitor to watch internal to external ac-
• Software Watchdog Timer (SWT) — The SWT asserts a reset or non-maskable
• Periodic Interrupt Timer (PIT) — The SIU provides a timer to generate periodic
• Power-PC Time Base Counter (TB) — The TB is a 64-bit counter defined by the
• Power-PC Decrementer (DEC) — The DEC is a 32-bit decrementing counter de-
cording to the particular requirements. The functions include control of show cycle
operation, pin multiplexing, and internal memory map location. System configura-
tion also includes a register containing part and mask number constants to iden-
tify the part in software.
from a number of internal and external sources and directs them on a single in-
terrupt-request line to the RCPU.
SGPIO pins are multiplexed with the address and data pins.
of operation that allow an alternate master on the external bus to access the in-
ternal modules for debugging and backup purposes.
cesses. It monitors the transfer acknowledge (TA) response time for internal to
external transfers. A transfer error acknowledge (TEA) is asserted if the TA re-
sponse limit is exceeded. This function can be disabled.
interrupt (as selected by the system protection control register) if the software fails
to service the SWT for a designated period of time (e.g, because the software is
trapped in a loop or lost). After a system reset, this function is enabled with a max-
imum time-out period and asserts a system reset if the time-out is reached. The
SWT can be disabled or its time-out period can be changed in the SYPCR. Once
the SYPCR is written, it cannot be written again until a system reset.
interrupts for use with a real-time operating system or the application software.
The PIT provides a period from 1 µs to 4 seconds with a 4-Mhz crystal or 200 ns
to 0.8 ms with a 20-Mhz crystal. The PIT function can be disabled.
MPC555 / MPC556 architecture to provide a time base reference for the operat-
ing system or application software. The TB has four independent reference reg-
isters which can generate a maskable interrupt when the time-base counter
reaches the value programmed in one of the four reference registers. The asso-
ciated bit in the TB status register will be set for the reference register which gen-
erated the interrupt.
SYSTEM CONFIGURATION AND PROTECTION
SYSTEM CONFIGURATION AND PROTECTION
Rev. 15 October 2000
SECTION 6
MOTOROLA
6-1