MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 519

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.8.7.8 Idle-Line Detection
MPC555
USER’S MANUAL
flag (NF), the parity flag (PF), and the framing error (FE) flag in SCxSR are not set until
data is transferred from the serial shifter to the RDRx.
RDRF must be cleared before the next transfer from the shifter can take place. If
RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR)
flag in SCxSR is set. OR indicates that the RDRx needs to be serviced faster. When
OR is set, the data in the RDRx is preserved, but the data in the serial shifter is lost.
When a completed frame is received into the RDRx, either the RDRF or OR flag is al-
ways set. If RIE in SCCxR1 is set, an interrupt results whenever RDRF is set. The re-
ceiver status flags NF, FE, and PF are set simultaneously with RDRF, as appropriate.
These receiver flags are never set with OR because the flags apply only to the data in
the receive serial shifter. The receiver status flags do not have separate interrupt en-
ables, since they are set simultaneously with RDRF and must be read by the user at
the same time as RDRF.
When the CPU reads SCxSR and SCxDR in sequence, it acquires status and data,
and also clears the status flags. Reading SCxSR acquires status and arms the clear-
ing mechanism. Reading SCxDR acquires data and clears SCxSR.
During a typical serial transmission, frames are transmitted isochronically and no idle
time occurs between frames. Even when all the data bits in a frame are logic ones, the
start bit provides one logic zero bit-time during the frame. An idle line is a sequence of
contiguous ones equal to the current frame size. Frame size is determined by the state
of the M bit in SCCxR1.
The SCI receiver has both short and long idle-line detection capability. Idle-line detec-
tion is always enabled. The idle-line type (ILT) bit in SCCxR1 determines which type
of detection is used. When an idle-line condition is detected, the IDLE flag in SCxSR
is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bit-
times whenever they occur. Short detection provides the earliest possible recognition
of an idle-line condition, because the stop bit and contiguous logic ones before and
after it are counted. For long idle-line detection, the receiver counts logic ones after the
stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, software overhead can cause a bit-time of logic level one to oc-
cur between frames. This bit-time does not affect content, but if it occurs after a frame
of ones when short detection is enabled, the receiver flags an idle line.
When the ILIE bit in SCCxR1 is set, an interrupt request is generated when the IDLE
flag is set. The flag is cleared by reading SCxSR and SCxDR in sequence. For receiv-
er queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a
read of SCRQ[0:15]. IDLE is not set again until after at least one frame has been re-
ceived (RDRF = 1). This prevents an extended idle interval from causing more than
one interrupt.
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MPC556
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
MOTOROLA
14-57