MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 361

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MPC555
USER’S MANUAL
The CSx timing is defined by the setup time required between the address lines and
the CE line. The memory controller allows the user to specify the CS timing to meet
the setup time required by the peripheral device. This is accomplished through the
ACS field in the base register. In
asserted half a clock cycle after the address lines are valid.
/
MPC556
Address
CLOCK
RD/WR
MPC555 / MPC556
Data
CS
TS
TA
Figure 10-8 Peripheral Devices Basic Timing
Figure 10-7 Peripheral Devices Interface
Address
RD/WR
Data
CSx
MEMORY CONTROLLER
(ACS = 11,TRLX = 0)
Rev. 15 October 2000
Figure
10-8, the ACS bits are set to 11, so CSx is
Address
CE
R/W
Data
Peripheral
ACS = 11
CSNT = 1
MOTOROLA
10-9

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