MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 220

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.5 Hardware Bus Monitor
6.6 MPC555 / MPC556 Decrementer
MPC555
USER’S MANUAL
The bus monitor ensures that each bus cycle is terminated within a reasonable period
of time. The USIU provides a bus monitor option to monitor internal to external bus ac-
cesses on the external bus. The monitor counts from transfer start to transfer acknowl-
edge and from transfer acknowledge to transfer acknowledge within bursts. If the
monitor times out, transfer error acknowledge (TEA) is asserted internally.
The bus monitor timing bit in the system protection control register (SYPCR) defines
the bus monitor time-out period. The programmability of the time-out allows for varia-
tion in system peripheral response time. The timing mechanism is clocked by the sys-
tem clock divided by eight. The maximum value is 2040 system clock cycles.
The bus monitor enable (BME) bit in the SYPCR enables or disables the bus monitor.
The bus monitor is always enabled, however, when freeze is asserted or when a de-
bug mode request is pending, regardless of the state of this bit.
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC555 /
MPC556 architecture to provide a decrementer interrupt. This binary counter is
clocked by the same frequency as the time base (also defined by the MPC555 /
MPC556 architecture). The operation of the time base and decrementer are therefore
coherent. In the MPC555 / MPC556, the DEC is clocked by the TMBCLK clock. The
decrementer period is computed as follows:
/
MPC556
15 (Lowest)
0 (Highest)
Priority
16-31
10
11
12
13
14
1
2
3
4
5
6
7
8
9
SYSTEM CONFIGURATION AND PROTECTION
Table 6-3 Priority of Interrupt Sources
Interrupt Source
Rev. 15 October 2000
Reserved
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt Code
00000000
00000100
00001000
00001100
00010000
00010100
00011000
00011100
00100000
00100100
00101000
00101100
00110000
00110100
00111000
00111100
—
MOTOROLA
6-12