MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 277

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.8.3.1 Exiting from Normal-Low Mode
8.8.3.2 Exiting from Doze Mode
8.8.3.3 Exiting from Deep-Sleep Mode
MPC555
USER’S MANUAL
decrementer exception is only three to four clock cycles of maximum system frequen-
cy. In 40-MHz systems, this wake-up requires 75 to 100 ns. The asynchronous wake-
up interrupt from the interrupt controller is level sensitive one. It will therefore be ne-
gated only after the reset of interrupt cause in the interrupt controller.
The timers (RTC, PIT, time base, or decrementer) interrupts indication set status bits
in the PLPRCR (TMIST). The clock module considers this interrupt to be pending
asynchronous interrupt as long as the TMIST is set. The TMIST status bit should be
cleared before entering any low-power mode.
Table 8-7
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system
toggles between low frequency (defined by PLPRCR[DFNL]) and high frequency (de-
fined by PLPRCR[DFNH]. The system switches from normal-low mode to normal-high
mode if either of the following conditions is met:
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asyn-
chronous interrupt status bits are reset, the system returns to normal-low mode.
The system changes from doze mode to normal-high mode whenever an interrupt is
pending from the interrupt controller.
The system switches from deep-sleep mode to normal-high mode if any of the follow-
ing conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
/
MPC556
summarizes wake-up operation for each of the low-power modes.
Normal-low (“gear”)
Operation Mode
Power-down
Deep-sleep
Doze-high
Doze-low
V
Table 8-6 Power Mode Wake-Up Operation
DDSRAM
Sleep
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
Wake-up
Software
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
External
Method
or
< 500 oscillator cycles + power
Return Time from Wake-up
3-4 maximum system cycles
3-4 maximum system clocks
Asynchronous interrupts:
3-4 actual system cycles
Synchronous interrupts:
Event to Normal-High
< 500 Oscillator Cycles
Power-on sequence
125 µsec – 4 MHz
25 µsec – 20 MHz
supply wake-up
MOTOROLA
8-17