MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 695

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

20.3.2 SRAM Test Register (SRAMTST)
SRAMTST — SRAM Test Register
MPC555
USER’S MANUAL
SRAMMCR — SRAM Module Configuration Register
20, 23, 26,
21, 24, 27,
22, 25, 28,
MSB
LCK
16
0
0
0
Bit(s)
RESET:
RESET:
3:19
The SRAM test register is used for factory testing only.
29
30
31
0
1
2
RESERVED
DIS
17
/
1
0
0
MPC556
(x = 0, 1, 2, 3)
(x = 0, 1, 2, 3)
(x = 0, 1, 2, 3)
2CY
18
Name
2
0
0
LCK
2CY
DIS
Rx
Dx
Sx
—
19
3
0
0
Lock bit. This bit can be set only once and cleared only by reset.
0 = Writes to the SRAMMCR are accepted
1 = Writes to the SRAMMCR are ignored
Module disable
0 = SRAM module is enabled
1 = SRAM module is disabled. Module can be subsequently re-enabled by software set-
Two-cycle mode
0 = SRAM module is in single-cycle mode (normal operation)
1 = SRAM module is in two-cycle mode. In this mode, the first cycle is used for decoding
Reserved
Read only. R0 controls the highest 4-Kbyte block (lowest address) of the SRAM array;
R3 controls the lowest block (highest address).
0 = 4-Kbyte block is readable and writable
1 = 4-Kbyte block is read only. Attempts to write to this space result in internal TEA as-
Data only. D0 controls the highest 4-Kbyte block (lowest address) of the SRAM array; D3
controls the lowest block (highest address).
0 = 4-Kbyte block can contain data or instructions
1 = 4-Kbyte block contains data only. Attempts to load instructions from this space result
Supervisor only. S0 controls the highest 4-Kbyte block (lowest address) of the SRAM ar-
ray; S3 controls the lowest block (highest address).
0 = 4-Kbyte block is placed in unrestricted space
1 = 4-Kbyte block is placed in supervisor space. Attempts to access this space from the
Table 20-1 SRAMMCR Bit Descriptions
STATIC RANDOM ACCESS MEMORY (SRAM)
R0
20
4
0
0
ting this bit or by reset. Attempts to read SRAM array when it is disabled result in
internal TEA assertion.
the address, and the second cycle is used for accepting or providing data. This
mode provides some power savings while keeping the memory active.
sertion.
in internal TEA assertion.
user privilege level result in internal TEA assertion.
D0
21
5
0
0
Rev. 15 October 2000
22
S0
6
0
0
R1
23
7
0
0
D1
24
8
0
0
RESERVED
Description
S1
25
9
0
0
R2
10
26
0
0
D2
11
27
0
0
0x38 0004, 0x38 000C
S2
12
28
0
0
R3
13
29
0
0
0x38 0000
0x38 0008
MOTOROLA
D3
14
30
0
0
LSB
S3
15
31
20-3
0
0