MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 173

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.4.15 Implementation-Specific Debug Interrupts
MPC555
USER’S MANUAL
Execution resumes at offset 0x01400 from the base address indicated by MSR
Implementation-specific debug interrupts occur in the following cases:
The following registers are set:
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Data/Storage Interrupt Status
Data Address Register (DAR)
• When there is an internal breakpoint match (for more details, refer to
• When a peripheral breakpoint request is asserted to the MPC555 / MPC556 core.
• When the development port request is asserted to the MPC555 / MPC556 core.
/
21 DEVELOPMENT
Refer to
the development port-interrupt request.
MPC556
Register (DSISR)
Register Name
SECTION 21 DEVELOPMENT SUPPORT
SUPPORT.
CENTRAL PROCESSING UNIT
10:15
Other
Other
Bits
7:31
ME
1:4
2:3
LE
IP
0
1
4
5
6
Rev. 15 October 2000
Set to the effective address of the instruction that caused the
interrupt
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
Bit is copied from ILE
Set to 0
Set to 0
Set to 0
Set to 0
Set to 1 if the storage access is not permitted by the protec-
tion mechanism. Otherwise set to 0
Set to 0
Set to 1 for a store operation and to 0 for a load operation
Set to 0
Set to the effective address of the data access that caused
the interrupt
RI
Description
for details on how to generate
MOTOROLA
SECTION
IP
.
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