MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 356

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.2.1 Associated Registers
10.2.2 Port Size Configuration
MPC555
USER’S MANUAL
A[0:16]
When a match is found on one of the memory banks, its attributes are selected for the
functional operation of the external memory access:
Note that if more than one region matches the internal address supplied, then the low-
est region is selected to provide the attributes and the chip select.
Status bits for each memory bank are found in the memory control status register
(MSTAT). The MSTAT reports write-protect violations for all the banks.
Each of the four banks has a base register (BR) and an option register (OR). The BRx
and ORx registers contain the attributes specific to bank x. The base register contains
a valid bit (V) that indicates that the register information for that chip select is valid.
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be ac-
cessed as odd or even bytes. Defined 16-bit ports, when connected to data bus lines
zero to 15, can be accessed as odd bytes, even bytes, or even half-words. Defined 32-
bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words,
• Read-only or read/write operation
• Number of wait states for a single memory access, and for any beat in a burst
• Burst-inhibit indication. Internal burst requests are still possible during burst-inhib-
• Port size of the external device
comp comp comp comp comp comp comp comp comp comp comp
RB A
[0]
/
access
ited cycles; the memory controller emulates the burst cycles
MPC556
RB A
[1]
RB A RB A
[2]
Figure 10-4 Bank Base Address and Match Structure
[3]
Base Address
RB A
[4]
O O O O O O O O O
MEMORY CONTROLLER
Rev. 15 October 2000
RB A
[15]
RB A
[16]
M
[0]
M[0:16]
M
[1]
Address Mask
M
[2]
M
[3]
M
[4]
M
Match
[5]
M
[6]
M
[7]
O O O O
MOTOROLA
M
[16]
10-4