MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 531

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
• Only data that has no errors (FE and PF both false) is allowed into the queue. The
• Queue size capable to receive up to 16 data frames (SCRQ[0:15]) which may al-
• Interrupt generation can occur when the top half (SCRQ[0:7]) of the queue has
• In order to implement the receive queue, the following conditions must be met:
• Enable and disable options for the interrupts QTHF and QBHF as controlled by
• 4-bit counter (QRPNT) is used as a pointer to indicate where the next valid data
• A queue overrun error flag (QOR) to indicate when the queue is already full when
• The queue can be exited when an idle line is used to indicate when a group of
• For receiver queue operation, IDLE is cleared when SC1SR is read with IDLE set,
• For receiver queue operation, NF is cleared when the SC1SR is read with NF set,
• The queue is successfully filled (16 data frames) if error flags (FE and PF) are
• QOR indicates that a new data frame has been received in the data register
/
Locations SCRQ[0:15] can be used as general purpose 9-bit registers. Software
should ignore all other bits pertaining to the queue.
status flags FE and PF, if set, reflect the status of data not allowed into the queue.
The receive queue is disabled until the error flags are cleared via the original SCI
mechanism and the queue is re-initialized. The pointer QRPNT indicates the
queue location where the data frame would have been stored.
low for infinite and continuous receives.
been filled (QTHF) and the bottom half (SCRQ[8:15]) of the queue has been filled
(QBHF). This may allow for uninterrupted and continuous receives by indicating
to the CPU to start reading the queue portion that is now full.
QRE must be set (QSCI1CR); RE must be set (SCC1R1); QOR and QTHF must
be cleared (QSCI1SR); and OR, PF, and FE must be cleared (SC1SR).
the QTHFI and QBHFI, respectfully.
frame will be stored.
another data frame is ready to be stored into the queue (similar to the OR bit in
single buffer mode). The QOR bit can be set for QTHF = 1 or QBHF = 1, depend-
ing on where the store is being attempted.
serial transmissions is finished. This can be achieved by using the ILIE bit to en-
able the interrupt when the IDLE flag is set. The CPU can then clear QRE and/or
RE allowing the receiver queue to be exited.
followed by a read of SCRQ[0:15].
followed by a read of SCRQ[0:15]. When noise occurs, the data is loaded into the
receive queue, and operation continues unaffected. However, it may not be pos-
sible to determine which data frame in the receive queue caused the noise flag to
be asserted.
clear, QTHF and QBHF are set, and QRPNT is reset to all zeroes.
(SC1DR), but it cannot be placed into the receive queue due to either the QTHF
or QBHF flag being set (QSCI1SR). Under this condition, the receive queue is dis-
abled (QRE = 0). Software may service the receive queue and clear the appropri-
— The QTHF bit is set by hardware when the top half is full. The QTHF bit is
— The QBHF bit is set by hardware when the bottom half is full. The QBHF bit is
MPC556
cleared when the SCxSR is read with QTHF set, followed by a write of QTHF
to zero.
cleared when the SCxSR is read with QBHF set, followed by a write of QBHF
to zero.
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
MOTOROLA
14-69