MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 599

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.5.2 Low-Power Stop Mode
MPC555
USER’S MANUAL
After engaging one of the mechanisms to place the TouCAN in debug mode, the user
must wait for the FRZACK bit to be set before accessing any other registers in the Tou-
CAN; otherwise unpredictable operation may occur.
To exit debug mode, the IMB FREEZE line must be negated or the HALT bit in
CANMCR must be cleared.
Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting
for 11 consecutive recessive bits before beginning to participate in CAN bus commu-
nication.
Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an
idle state, or for the third bit of intermission to be recessive. The TouCAN then waits
for the completion of all internal activity (except in the CAN bus interface) to be com-
plete. Then the following events occur:
To exit low-power stop mode:
When the TouCAN is in low-power stop mode, a recessive to dominant transition on
the CAN bus causes the WAKEINT bit in the error and status register (ESTAT) to be
set. This event generates an interrupt if the WAKEMSK bit in CANMCR is set.
Consider the following notes regarding low-power stop mode:
• The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving
• The bus interface unit continues to operate, allowing the CPU to access the mod-
• The TouCAN ignores its Rx pins and drives its Tx pins as recessive
• The TouCAN loses synchronization with the CAN bus, and the STOPACK and
• Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting
• Clear the STOP bit in CANMCR.
• The TouCAN module can optionally exit low-power stop mode via the self wake
• When the self wake mechanism is activated, the TouCAN tries to receive the
• If the STOP bit is set while the TouCAN is in the bus off state, then the TouCAN
• To place the TouCAN in low-power stop mode with the self wake mechanism
/
maximum power savings
ule configuration register
NOTRDY bits in the module configuration register are set
the SOFTRST bit CANMCR.
mechanism. If the SELFWAKE bit in CANMCR was set at the time the TouCAN
entered stop mode, then upon detection of a recessive to dominant transition on
the CAN bus, the TouCAN clears the STOP bit in CANMCR and its clocks begin
running.
frame that woke it up. (It assumes that the dominant bit detected is a start-of-
frame bit.) It will not arbitrate for the CAN bus at this time.
enters low-power stop mode and stops counting recessive bit times. The count
continues when STOP is cleared.
engaged, write to CANMCR with both STOP and SELFWAKE set, and then wait
MPC556
CAN 2.0B CONTROLLER MODULE
Rev. 15 October 2000
MOTOROLA
16-17